Verilog HDL????

    ??

    b?????

    ?????????д???

    (2)??

    ?b = a;

    ?????

    b????????

    ???

    ??????????“always”?reg?????????????е“always”??reg??????

    b <= a;

    ?????е???“always”???кba???“always”???и????????

    b = a;

    ????е??????b?a?????鷳?

1?

always @ posedge clk begin

      b<=a;

      c<=b;

end

1е“always”???reg?bcclk????b?ac?b??????“always”?е?c???b?“always”??·?1?

2??

always @posedge  clk begin

      b=a;

      c=b;

end

2е“always”??clk????μ?仯b?a?c?b?a???·?2?

                      ?1  ???·                  ?2  ???·

 ???a???bc????3.5???????

??????????begin_end?????е?????飻?fork_join????е????п顣???

1?

???

1????е?????С

2?????????

3??????顣

???￡

begin

1;

2;

......

n;

end

?

begin:

1;

2;

......

n;

end

У

1????ú??

2??reg??integer?real??

?

3?顣

begin

areg = breg;

creg = areg;  //creg??breg?

end

?????Уareg??breg???????creg??areg?????κ???creg???breg???????????4?

4??顣

begin

areg = breg;

#10 creg = areg;   //??10??λ

end

• 1
• 2
• ??

• ?? Verilog HDL???
• ?? ????????