Verilog HDL???·

ifrst == 1’b0   Dout <= 1’b0;

else Dout   <= Din;                            //D

1У??clock??Dout???Din?λ????Dout??0????·У??÷??“<=”always???￡磺

2?λD2

wire Din;

wire clock,rst;

reg Dout;

always @ posedge clock or negedge rst   //?λ

ifrst == 1’b0   out <= 1’b0;

else begin

Dout <= Din;                         //D???

Dout <= 1’b1;                        //D????

End                                         //D?1

2УDout???Din?Dout??з??Dout???1?Dout??????always??Dout?????Dout??1

??·Уalways?????????м?ù?“or”?磺

always @posedge clock or posedge reset begin     //?always

…

end

??????λ??

always @posedge clock1 or posedge clock2 or posedge reset begin

//3?always

…

end

?????λ??

?????·??龡????

• ?? ????????
• ?? Verilog HDL???