Verilog HDL??--?

Verilog HDL??·??Verilog HDL?·???·Verilog HDL??Verilog HDL????????????·?????·Verilog HDL??Verilog????·???Щ?????5?

• ??system??????????
• ?algorithm????????
• RTLRegister Transfer Level???δЩ???
• ?gate-level???????
• ?switch-level????????

??·??Verilog HDL??Verilog HDL?鹹????????鹹ɡЩ?????·Щ?????齻?·??Verilog HDL?????????ν?临?????·??

Verilog HDL?????????????RTL????1?

• ??л?е??
• ???????????
• ???????
• ?if-elsecase??
• ?????task?
• ???μ???function
• ????λ
• Verilog HDL???????????????1?
  • ????primitive
  • ???·???
  • ?MOS???????

Verilog HDL?????????Verilog HDLУ????????????????в????趨?Χ??????

Verilog HDL??????C??if?case?Cе?????C??????Verilog HDL???Verilog HDL?Щ????????????·潫Verilog HDLе???

Verilog HDL

Verilog HDL?зVerilog HDL?

1?

module  adder count,sum,a,b,cin ;  //???

     input 2:0 a,b;                        //??

     input  cin;

     output  count;

     output 2:0 sum;

     assign {count,sum} = a + b + cin;     //???

endmodule

????adderλ??ab?λcin?sum?λcountп?Verilog HDL?moduleendmodule?

2?

module  compare equal,a,b ;    //???

         output  equal;                //?equal

         input 1:0 a,b;             //?ab

         assign  equal=a==b10; //ab ?,?1,?0

endmodule

????compare??abб??ab?equal??????У“/*........*/”“//.........”???????????????

3???

module  trist2out,in,enable;     //???

     output  out;                      //??

     input  in, enable;

     bufif1  mybufout,in,enable;  //??bufif1

endmodule

??trist2???Verilog?????bufif1?书?

4??

module  trist1out,in,enable;    //???

     output  out;                      //??

     input  in, enable;

     mytri  tri_instout,in,enable;//?mytri?鶨??tri_inst

endmodule

     module  mytriout,in,enable; //???

     output  out;                          //??

     input  in, enable;

     assign  out = enable? in : 'bz;   //??

endmodule

??????д?顣?trist1?mytri??tri_inst?trist1??顣?mytri????顣

???

• Verilog HDL?鹹??????moduleendmodule???????????в????,????·????С????,????幦?
• ???ж??,?,??????
• Verilog HDLд?,?пд,???дС
• endmodule,??з??
• “/*.....*/”“//.......”Verilog HDLκβ??????ü??????,???????

??

??I/OI/O?????塣

1I/O

???????￡

Module    ??1?2?3?4, …;

2I/O?

I/O???￡

?input  ?1?2…?i  //i?

?output ?1?2…?j      //j?

I/O??д????￡

module  module_nameinput port1,input port2,…,output port1,output port2…

3??

????й?wirereg?

reg width-1 : 0 R1R2 …

wire width-1 : 0 W1W2 …

4?

?????岿?3??в?

1“assign”?

assign a = b & c;

???????д?“assign”???ɡе????

2??

and and_inst q, a, b ;

????·???￡?????????and??and_inst??ab?q?????Ω????and?

3“always”顣

always @posedge clk or posedge clr begin        //???

   ifclr  q <= 0;                              //

   else  ifen q <= d;                          //???

   end

“assign”??????“always”?????“always”???D

“always”ú???о“if...else”??簴??д“always”飬??????????????·???Verilog??????Щ???Щ??

3??“assign”???“always”顣3????е???3д?Verilog?????????????3???е????

?“always”???????е?“always”е?“?”???е???“always”?????е?????е?

?“always”???????“if…else… if”??У书??κ塣elseif???У????????“always”??佫д??С

• 1
• 2
• ??

• ?? ?岦???
• ?? Verilog HDLC??